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S3CB018/fb018 product overview 1- 1 1 product overview calmrisc overview the S3CB018/fb018 single-chip cmos microcontroller is designed for high performance using samsung ? s newest 8-bit cpu core, calmrisc. calmrisc is an 8-bit low power risc microcontroller. its basic architecture follows harvard style, that is, it has separate program memory and data memory. both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access. represented below is the top block diagram of the calmrisc microcontroller.
product overview S3CB018/fb018 1- 2 S3CB018/fb018 overview features summary cpu 8-bit risc architecture memory rom: 4 kword (8 k-byte) ram: 3072 (1024+2048) byte 1024 (x-memory) byte 2048 (y-memory) byte stack size: maximum 16 (word)-level 26 i/o pins i/o: 26 pins, including 8 s/w open drain pins 8-bit basic timer programmable interval timer 8 kinds of clock source watchdog timer system reset when 11-bit counter overflows 16-bit timer/counter programmable interval timer two 8-bit timer counter mode and one 16-bit timer counter mode, selectable by s/w watch timer real time clock or interval time measurement four frequency outputs for buzzer sound 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode lsb first or msb first transmission selectable internal and external clock source 16-bit serial i/o interface 16-bit transmit/receive mode external clock source coprocessor mac 816 8 x 16, 16 x 16 multiply and accumulation arithmetic operation two power-down modes idle mode: only cpu clock stop stop mode: selected system clock and cpu clock stop oscillation sources crystal and ceramic (0.4-20mhz), rc oscillation programmable oscillation source instruction execution times 50ns at 20mhz for 1 cycle instruction 100ns at 20mhz for 2 cycle instruction
S3CB018/fb018 product overview 1- 3 bbus[7:0] 20 program memory address generation unit pc[19:0] hardware stack hs[0] hs[15] 8 8 r0 r3 r1 r2 alu abus[7:0] alul alur pa[19:0] pd[15:0] idl0 idl1 sr0 sr1 ilh ilx ill spr idh do[7:0] di[7:0] gpr data memory address generation unit da[15:0] 20 flag rbus tbh tbl bank 0,1 figure 1-1. top block diagram of calmrisc
product overview S3CB018/fb018 1- 4 the calmrisc building blocks consist of: ? an 8-bit alu ? 16 general purpose registers (gpr) ? 11 special purpose registers (spr) ? 16-level hardwa re stack ? program memory address generation unit ? data memory address generation unit 16 gpr ? s are grouped into four banks (bank0 to bank3) and each bank has four 8-bit registers (r0, r1, r2, and r3). spr ? s, designed for special purposes, include status registers, link registers for branch-link instructions, and data memory index registers. the data memory address generation unit provides the data memory address (denoted as da[15:0] in the top block diagram) for a data memory access instruction. data memory contents are accessed through di[7:0] for read operations and do[7:0] for write operations. the program memory address generation unit contains a program counter, pc[19:0], and supplies the program memory address through pa[19:0] and fetches the corresponding instruction through pd[15:0] as the result of the program memory access. calmrisc has a 16-level hardware stack for low power stack operations as well as a temporary storage area. calmrisc has a 3-stage pipeline as described below: instruction fetch (if) instruction decode/ data memory access (id/mem) execution/writeback (exe/wb) figure 1-2. calmrisc pipeline diagram as can be seen in the pipeline scheme, calmrisc adopts a register-memory instruction set. in other words, data memory where r is a gpr, can be one operand of an alu instruction as shown below: the first stage (or cycle) is instruction fetch stage (if for short), where the instruction pointed to by the program counter, pc[19:0] , is read into the instruction register (ir for short). the second stage is instruction decode and data memory access stage (id/mem for short), where the fetched instruction (stored in ir) is decoded and data memory access is performed, if necessary. the final stage is execute and write-back stage (exe/wb), where the required alu operation is executed and the result is written back into the destination registers. since calmrisc instructions are pipelined, the next instruction fetch is not postponed until the current instruction is completely finished, but is performed immediately after the current instruction fetch is done. the pipeline stream of instructions is illustrated in the following diagram.
S3CB018/fb018 product overview 1- 5 exe/wb if if if if if if if id/mem id/mem id/mem id/mem id/mem id/mem exe/wb exe/wb exe/wb exe/wb exe/wb / 1 / 2 / 3 / 4 / 6 / 5 figure 1-3. calmrisc pipeline stream diagram most calmrisc instructions are 1-word instructions, while same branch instructions such as ? lcall ? and ? ljt ? instructions are 2-word instructions. in figure 1-3, the instruction, i 4 , is a long branch instruction and it takes two clock cycles to fetch the instruction. as indicated in the pipeline stream, the number of clocks per instruction (cpi) is 1 except for long branches, which take 2 clock cycles per instruction.
product overview S3CB018/fb018 1- 6 calmrisc cpu osc control wt bt/wdt mac 816 control register 128 byte (38 byte) p3.0 - p3.1 p2.0 - p2.7 p1.0 - p1.7 p0.0 - p0.7 port 3 port 2 port 1 port 0 timer a timer b sio sio si s0 sck taclk taout tbclk tbout adda x-memory 1024 byte y-memory 2048 byte figure 1-4. S3CB018/fb018 block diagram
S3CB018/fb018 product overview 1- 7 pin assignments S3CB018 32-sop (top-view) v ss x o ut x i n test si/p0.0 so/p0.1 reset sck/p0.2 buz/p0.3 csi/p0.4 cso/p0.5 csck/p0.6 cfsync/p0.7 p1.0 p1.1 p1.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p3.1/sclk/int01 p3.0/sdat/int00 p2.7/taclk p2.6/tbout p2.5/tbclk p2.4/taout p2.3/int13 p2.2/int12 p2.1/int11 p2.0/int10 p1.2 p1.3 p1.4 p1.5 p1.6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 1-5. 32-sop pin assignment v dd p3.1/sclk/int01 p3.0/sdat/int00 p2.7/taclk p2.6/tbout p2.5/tbclk p2.4/taout p2.3/int13 p2.2/int12 p2.1/int11 p2.0/int10 p1.2 p1.3 p1.4 p1.5 S3CB018 30-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 v ss x o ut x i n test si/p0.0 so/p0.1 reset sck/p0.2 buz/p0.3 csi/p0.4 cso/p0.5 csck/p0.6 cfsync/p0.7 p1.0 p1.1 figure 1-6. 30-sdip pin assignment
product overview S3CB018/fb018 1- 8 i/o pin description table 1-1. S3CB018/fb018 pin descriptions (32-sop) pin name pin type pin description circuit type share pins p0.0-p0.7 i/o i/o port with bit programmable pins; input and output mode are selectable by software; software assignable pull-up. p0.4-p0.7 can be used as inputs for comparator input cin0-cin3.; alternately they can be used as si, so, sck, buz, csi, cso, csck, cfsync. d-2 f-10 si, so, sck buz, csi, cso, csck, cfsync p1.0-p1.7 o output port with bit programmable pins; push-pull output mode and open-drain output mode are selected by software; software assignable pull-up. e-2 p2.0-p2.7 i/o i/o port with bit programmable pins; input and output mode are selectable by software; software assignable pull-up; p2.0-p2.3 can be used as inputs for external interrupts int10-int13. (with noise filter) ; alternately they can be used as taout, taclk or tbout, tbclk. d-4 d-2 int10-int13 taout taclk tbout tbclk p3.0-p3.1 i/o i/o port with bit programmable pins; input or output mode selected by software; software assignable pull-up; p3.0-p3.1 can be used as inputs for external interrupts int00-int01. (with noise filter and interrupt polarity control) d-4 int00-int01 table 1-2. S3CB018/fb018 pin descriptions (30-sdip) pin name pin type pin description circuit type share pins p0.0-p0.7 i/o i/o port with bit programmable pins; input and output mode are selectable by software; software assignable pull-up. p0.4-p0.7 can be used as si, so, sck, buz, csi, cso, csck, cfsync, alternately. d-2 f-10 si, so, sck buz, csi, cso, csck, cfsync p1.0-p1.5 o o port with bit programmable pins; push-pull output mode and open-drain output mode are selected by software; software assignable pull-up. e-2 p2.0-p2.7 i/o i/o port with bit programmable pins; input and output mode are selectable by software; software assignable pull-up; p2.0-p2.3 can be used as inputs for external interrupts int10-int13. (with noise filter); alternately they can be used as taout, taclk or tbout, tbclk. d-4 d-2 int10-int13 taout taclk tbout tbclk p3.0-p3.1 i/o i/o port with bit programmable pins; input or output mode selected by software; software assignable pull-up; p3.0-p3.1 can be used as inputs for external interrupts int00-int01. (with noise filter and interrupt polarity control) d-4 int00-int01 note: in S3CB018/fb018, the csi, cso, csck, cfsync pins are shared with p0.7-p0.4.
S3CB018/fb018 product overview 1- 9 table 1-3. i/o pin description pin name pin type description csi i ad/da serial input (from codec) cso o ad/da serial output (to codec) csck i ad/da serial clock (from codec) cfsync i ad/da sync signal (from codec) si i/o serial data input so i/o serial data output sck i/o serial i/o interface clock signal buz i/o 0.5 khz, 1 khz, 2 khz, or 4 khz frequency output at 4.19 mhz for buzzer sound int10-int13 i external interrupts. stop release. can ? t be masked by s/w individually but wholly. taout i/o timer a interval mode output taclk i/o timer a counter external clock input tbout i/o timer b interval mode output tbclk i/o timer b counter external clock input int00-int01 i external interrupts. stop release. can be masked by s/w individually. sdat i serial data for programmable memory sclk i serial clock for programmable memory vdd ? power supply vss ? ground test ? test signal input reset i reset signal x in , x out ? crystal, ceramic and rc oscillator signal for system clock (for external clock input, use x in and input x in 's reverse phase to x out )
product overview S3CB018/fb018 1- 10 pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p0.0 p0.1 p0.2 v dd p0.3 p0.4 p0.5 gnd p0.6 p0.7 v dd p1.0 p1.1 p1.2 p1.3 gnd p1.4 p1.5 p1.6 p1.7 gnd x in xout v ddi /v dd p2.0 p2.1 p2.2 v dd p2.3 p2.4 gnd p2.5 p2.6 p2.7 v dd p3.0 p3.1 gnd tmode pin_resb xda4 xda5 xda6 gnd xda7 xda8 xda9 v dd /v ddi xda10 xda11 xda12 xda13 gnd test pa0 pa1 pa2 v dd /v ddi pa3 pa4 pa5 gnd pa6 pa7 v dd pa8 pa9 pa10 pa11 gnd pa12 pa13 pa14 pa15 v dd pa16 pa17 pa18 pa19 bkreqx iclko gnd pd0 pd1 pd2 pd3 gnd pd4 pd5 pd6 pd7 v dd /v ddi pd8 pd9 pd10 gnd pd11 pd12 pd13 v dd /v ddi pd14 pd15 gnd np64kw xdocnt docntx outdis v dd runst npmcs npmoe npmwe gnd ptdo_txd ptdi_rxd ptms ptck_mclk v dd /v ddi pntrst_stateinit jtagsel xda3 xda2 xda1 xda0 v dd xd0 xd1 xd2 xd3 gnd xd4 xd5 xd6 xd7 v dd xd8 xd9 xd10 gnd xd11 xd12 xd13 xd14 xd15 v dd /v ddi csnxh csnxl wenx oenx gnd csnwio csnbio evenio wenio oenio v dd csin csclk cfsync csout s3eb010 160-qfp (top-view) figure 1-7. s3eb010 pin diagram
S3CB018/fb018 product overview 1- 11 table 1-4. evaluation chip pin descriptions no. pin name pin type description 1-3 5-9 p0.0-p0.2 p0.3-p0.7 i/o port 0 12-15 17-20 p1.0-p1.3 p1.4-p1.7 o port 1 22 x in i clock in 23 x out o clock out 25-27 29, 30 32, 34 p2.0-p2.2 p2.3, p2.4 p2.5-p2.7 i/o port 2 36, 37 p3.0, p3.1 i/o port 3 39 tmode i test mode pin; 1: skip warm-up time, 0: normal mode 40 pin_resb i asynchronous reset, active low 41 jtagsel i jtag mode select; 1: parallel, 0: serial 42 pntrst_ststeini t i jtag/uart pin 44 ptck_mclk i jtag/uart pin 45 ptms i jtag/uart pin 46 ptdi_rxd i jtag/uart pin 47 ptdo_txd o jtag/uart pin 49 npmwe o program memory write enable, active low 50 npmoe o program memory output enable, active low 51 npmcs o program memory chip select, active low 52 runst o run status indicator 54 outdis i i/o pad disable for debugger 55 docntx i data bus output control 56 xdocntx i external x-memory data bus output control 57 npm64kw i up to 64kw program memory, active low 59, 60 62-64 66-68 70-73 75-78 pd15-pd14 pd13-pd11 pd10-pd8 pd7-pd4 pd3-pd0 i/o program memory data bus
product overview S3CB018/fb018 1- 12 table 1-4. evaluation chip pin descriptions (continued) no. pin name pin type description 80 iclko o iclk output 81 bkreqx i break input for debugger 82-85 87-90 92-95 97, 98 100-102 104-106 pa19-pa16 pa15-pa12 pa11-pa8 pa7, pa6 pa5-pa3 pa2-pa0 o program memory address 107 test i test pin for debugger 109-112 114-116 118-124 xda13-xda10 xda9-xda7 xda6-xda0 o external x-memory address 126-129 131-134 136-138 140-144 xd0-xd3 xd4-xd7 xd8-xd10 xd11-xd15 i/o external x-memory data bus 146 csnxh o external x-memory high byte chip select, active low 147 csnxl o external x-memory low byte chip select, active low 148 wenx o external x-memory write enable, active low 149 oenx o external x-memory output enable, active low 151 csnwio o external i/o word chip select, active low 152 csnbio o external i/o byte chip select, active low 153 evenio o external i/o even indicator; 1:even, 0: odd 154 wenio o external i/o write enable, active low 155 oenio o external i/o output enable, active low 157 csin i ad / da serial input (from codec) 158 csclk i ad / da serial clock (from codec) 159 cfsync i ad / da sync signal (from codec) 160 csout o ad / da serial output (to codec) vdd power supply ? 4, 11, 24, 28, 35, 43, 53, 61, 69, 86, 96, 103, 113 125, 135, 145, 156 gnd ground ? 8, 16, 21, 31, 38, 48, 58, 65, 74, 79, 91, 99, 108, 117 130, 139, 150
S3CB018/fb018 product overview 1- 13 pin circuit diagrams schmitt trigger in v dd pull-up resistor figure 1-8. pin circuit type b ( reset ) p-channel n-channel v dd out output disable data figure 1-9. pin circuit type c p-channel i/o output disable data circuit type c pull-up enable v dd figure 1-10. pin circuit type d-2 (p0.0-p0.3, p2.4-p2.7) p-channel i/o output disable data circuit type c pull-up enable v dd schmitt trigger noise filter ext. int input figure 1-11. pin circuit type d-4 (p2.0-p2.3, p3)
product overview S3CB018/fb018 1- 14 p-channel n-channel v dd out open-drain enable data figure 1-12. pin circuit type e-2 (p1) pull-up enable circuit type c data output disable comparator enable reserved input v dd i/o figure 1-13. pin circuit type f-10 (p0.4-p0.7)
S3CB018/fb018 elect rical data 18- 1 18 electrical data overview table 18-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.0 v input voltage v i ? ? 0.3 to v dd + 0.3 output voltage v o ? ? 0.3 to v dd + 0.3 output current i oh one i/o pin active ? 18 ma high all i/o pins active ? 60 output current i ol one i/o pin active + 30 low total pin current for ports 1, 2, 3 + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 table 18-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage (hsx mode) v dd f cpu = 20 mhz 4.5 ? 5.5 v f cpu = 3 mhz 1.8 5.5 operating voltage (msx mode) v dd f cpu = 10 mhz 4.5 ? 5.5 f cpu = 3 mhz 1.8 5.5
electrical data s3c 18- 2 (t a = 40 c, v = 1.8 v to 5.5 v) parameter conditions min max unit v ih1 ih2 0.8 v ? dd v ih2 x v dd - 0.1 input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v il2 x in 0.1 output high voltage v oh1 v dd = 5v; i oh = -1 ma all output pins v dd -1.0 ? ? v output low voltage v ol1 v dd = 5v; i ol = 8 ma all output pins except v ol2 ? 2 v ol2 v dd = 5v; i ol = 15 ma, port 1 2 input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 3 ua i lih2 v in = v dd x in , xt in 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? -3 i lil2 v in = 0 v x in , xt in , reset -20 output high leakage current i loh v out = v dd all i/o pins and output pins ? ? 3 ua output low leakage current i lol v out = 0 v all i/o pins and output pins ? ? -3 oscillator feed back resistors r osc1 (hsx) v dd = 5.0 v, t a = 25 c, x in = v dd , x out = 0v 510 710 910 k w r osc2 (msx) v dd = 5.0 v,t a = 25 c, x in = v dd , x out = 0v 510 710 910 r osc3 (lsx) v dd = 5.0 v, t a = 25 c, x in = v dd , x out = 0v 2.0 2.7 3.5 m w pull-up resistor r l1 v in = 0 v; v dd = 5 v 10% ports 0,1,2,3,4,5 t a =25 c 30 50 70 k w r l2 v in = 0 v; v dd = 5 v 10% t a =25 c, reset only 110 210 310
S3CB018/fb018 elect rical data 18- 3 table 18-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 (2) operating mode: v dd = 5 v 10% 20 mhz crystal oscillator(hsx) ? 10 20 ma 5 mhz crystal oscillator(msx) 4 8 v dd = 3 v 10% 5 mhz crystal oscillator(msx) 2 4 i dd2 (3) idle mode: v dd = 5 v 10% 20 mhz crystal oscillator(hsx) ? 2.5 5 ma 5 mhz crystal oscillator(msx) 1 2 v dd = 3 v 10% 5 mhz crystal oscillator(msx) 0.4 0.8 i dd3 stop mode v dd = 5 v 10% ? 0.5 3 ua v dd = 3 v 10% 0.2 1.2 notes: 1. supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. in operating current test mode timer a and timer b are running. 3. in idle current test mode the watch timer is running. 4. the operating and idle currents are measured at weak mode . table 18-3. a. c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl p2.0 - p2.3, p3.0 - p3.1 v dd = 5v 200 ? ? ns reset input low width t rsl v dd = 5v 10% 1 ? ? us note: user must keep a value larger than the min value.
electrical data s3c b018/fb018 18- 4 t inth t intl 0.8 v dd 0.2 v dd figure 18-1. input timing for external interrupts reset t rsl 0.2 v dd figure 18-2. input timing for reset
S3CB018/fb018 elect rical data 18- 5 table 18-4. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5v) parameter symbol conditions min typ max unit data retention supply voltage v dddr 1.5 ? 5.5 v data retention supply current i dddr v dddr = 1.5v ? ? 2 a note: supply current does not include current drawn through internal pull-up resistors or external output current loads. execution of stop instruction reset occur ~ ~ v dddr ~ ~ stop mode normal operating mode data retention mode t wait reset v dd note: t wait is the same as 2048 x 32 x 1/fxx oscillation stabilization time 0.2v dd figure 18-3. stop mode release timing when initiated by a reset
electrical data s3c b018/fb018 18- 6 execution of stop instruction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode osc start up time t wait note: t wait is the same as 2048 x 32 x 1/fxx. the value of 2048 which is selected for the clock source of the basic timer counter can be changed. then the value of t wait will be changed and ,when you select 16 instead of 32, the value of twait will also be changed. oscillation stabilization time 0.2v dd int figure 18-4. stop mode release timing when initiated by interrupts
S3CB018/fb018 elect rical data 18- 7 table 18-5. synchronous sio electrical characteristics (t a = ? 40 c to + 85 c v dd = 4.5 v to 5.5 v, v ss = 0 v, fxx = 10 mhz oscillator ) parameter symbol conditions min typ max unit sck cycle time t cyc ? 200 ? ? ns serial clock high width t sckh ? 60 ? ? serial clock low width t sckl ? 60 ? ? serial output data delay time t od ? ? ? 50 serial input data setup time t id ? 40 ? ? serial input data hold time t ih ? 100 ? ? output data input data sck t sckh t cyc t sckl 0.8 v dd 0.2 v dd t od t id t ih 0.8 v dd 0.2 v dd si so figure 18-5. serial data transfer timing
electrical data s3c b018/fb018 18- 8 table 18-6. main oscillator frequency (t a = -40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal x in c1 c2 x out lsx mode 32 32.768 35 khz msx mode 0.4 ? 10 mhz hsx mode 0.4 ? 20 ceramic x in c1 c2 x out lsx mode 32 32.768 35 khz msx mode 0.4 ? 10 mhz hsx mode 0.4 ? 20 external clock x in x out lsx mode 32 32.768 35 khz msx mode 0.4 ? 10 mhz hsx mode 0.4 ? 20 rc r = 22kohm, v dd = 5 v direct soldering 1.4 2 2.6 mhz notes: 1. keep the wiring length as short as possible. 2. do not cross the wiring with the other signal lines. 3. do not route the wiring near a signal line through which a high fluctuating current flows. 4. always make the ground point of the oscillator capacitor the same potential as v ss . 5. do not ground the capacitor to a gro und pattern through which a high current flows. 6. do not fetch signals from the oscillator.
S3CB018/fb018 elect rical data 18- 9 frequency [khz] 2v 3v 4v 5v 5.5v 6v v dd [v] 1.8 0 500 1000 1500 2000 3000 2500 15k 22k 30k 33k 36k 62k 120k 180k 300k 82k figure 18-6. rc oscillator characteristic curve
electrical data s3c b018/fb018 18- 10 table 18-7. main oscillator oscillation stabilization time (t st1 ) (t a = -40 c + 85 c, v dd = 4.5 v to 5.5 v) oscillator test condition(normal mode) min typ max unit hsx crystal v dd = minimum oscillation voltage range. ? ? 10 ms ceramic ? ? 4 ms external clock x in input high and low level width (t xh , t xl ) 50 ? ? ns msx crystal v dd = minimum oscillation voltage range. ? ? 100 ms ceramic ? ? 50 ms external clock x in input high and low level width (t xh , t xl ) 50 ? ? ns lsx 32768hz crystal v dd = minimum oscillation voltage range. ? 200 500 ms note: oscillation stabilization time (t st1 ) is the time that is required to stabilize oscillation after a reset or stop mode release. x in t xh t xl 1/fosc1 v dd - 0.1 v 0.1 v figure 18-7. clock timing measurement at x in
S3CB018/fb018 elect rical data 18- 11 20 mhz f cpu 3 mhz 0.4 mhz 1 2 3 4 5 6 7 supply voltage (v) minimum instruction clock = 1/1 x oscillator frequency 5.5 4.5 1.8 a b 10 mhz figure 18-8. hsx mode operating voltage range 10 mhz f cpu 3 mhz 0.4 mhz 1 2 3 4 5 6 7 supply voltage (v) minimum instruction clock = 1/1 x oscillator frequency 5.5 4.5 1.8 a b figure 18-9. msx mode operating voltage range
S3CB018/fb018 mecha nical data 19- 1 19 mechanical data overview the S3CB018/fb018 is available in a 30-pin sdip package ( samsung: 30-sdip-400) and a 32-pin sop package (32 -sop-450a). package dimensions are shown in figures 20-1 and 20-2. note : dimensions are in millimeters. 27.88max 27.48 0 .2 1.778 (1.30) 0.51 min 3.30 0.3 3.81 0.2 5.08 max 0-15 1.12 0.1 0.25 + 0.1 - 0.05 10.16 #30 #16 #15 #1 30-sdip-400 0.56 0.1 8.94 0.2 figure 19-1. 30-pin sdip package dimensions
mechanical data s3c b018/fb018 19- 2 32-sop-450a #1 #16 #17 #32 2.40 max (0.43) 0.05 min 1.27 note: dimensions are in millimeters 19.90 0 .2 0.40 0 .1 12.00 0 .3 2.00 0 .2 11.43 0-8 8.34 0 .2 0.78 0 .2 0.20 + 0.1 - 0.05 figure 19-2. 32-sop-450a package dimensions
S3CB018/fb018 s3fb0 18 20- 1 20 s3fb018 flash mcu overview the s3fb018 single-chip cmos microcontroller is the flash version of the S3CB018 microcontroller. it has an on-chip flash rom instead of masked rom. the flash rom is accessed in serial data format. the s3fb018 is fully compatible with the S3CB018, both in function and in pin configuration. because of its simple programming requirements, the s3fb018 is ideal for use as an evaluation chip for the S3CB018.
s3fb018 S3CB018/fb0 18 20- 2 pin assignments s3fb018 32-sop (top-view) v ss x o ut x i n v pp /test si/p0.0 so/p0.1 reset / reset sck/p0.2 buz/p0.3 csi/p0.4 cso/p0.5 csck/p0.6 cfsync/p0.7 p1.0 p1.1 p1.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd p3.1/int01 / sclk p3.0/int00/ sdat p2.7/taclk p2.6/tbout p2.5/tbclk p2.4/taout p2.3/int13 p2.2/int12 p2.1/int11 p2.0/int10 p1.2 p1.3 p1.4 p1.5 p1.6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 20-1. 32-sop pin assignment v dd p3.1/int01/ sclk p3.0/int00/ sdat p2.7/taclk p2.6/tbout p2.5/tbclk p2.4/taout p2.3/int13 p2.2/int12 p2.1/int11 p2.0/int10 p1.2 p1.3 p1.4 p1.5 s3fb018 30-sdip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 v ss x o ut x i n v pp /test si/p0.0 so/p0.1 reset / reset sck/p0.2 buz/p0.3 csi/p0.4 cso/p0.5 csck/p0.6 cfsync/p0.7 p1.0 p1.1 figure 20-2. 30-sdip pin assignment
S3CB018/fb018 s3fb0 18 20- 3 table 20-1. descriptions of pins used to read/write the flash rom main chip during programming pin name pin name pin no. i/o function p3.0 sdat 30(28) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push- pull output port. p3.1 sclk 31(29) i/o serial clock pin. input only pin. test vpp (test) 4 i power supply pin for flash rom cell writing (indicates that flash enters into the writing mode). when 12.5 v is applied, flash is in writing mode and , when 5 v is applied, flash is in the reading mode. when flash is operating , hold gnd. reset reset 7 i chip initialization v dd /v ss v dd /v ss 32/1(30/1) ? logic power supply pin. v dd should be tied to +5 v during programming. note: pin no. is for 100 qfp type package. (for 100 tqfp, the pins with the same name have same functions). table 20-2. comparison of s3fb018 and S3CB018 features characteristic s3fb519 s3cb519 program memory 4k word (8k byte) flash rom 4k word (8k byte) flash rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 32-sop/30-sdip 32-sop/30-sdip flash rom programmability user programmable programmed at the factory
s3fb018 S3CB018/fb0 18 20- 4 table 20-3. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.0 v input voltage v i ? ? 0.3 to v dd + 0.3 output voltage v o ? ? 0.3 to v dd + 0.3 output current i oh one i/o pin active ? 18 ma high all i/o pins active ? 60 output current i ol one i/o pin active + 30 low total pin current for ports 1, 2, 3 + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 table 20-4. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage (hsx mode) v dd f cpu = 20 mhz 4.5 ? 5.5 v f cpu = 3 mhz 1.8 5.5 operating voltage (msx mode) v dd f cpu = 10 mhz 4.5 ? 5.5 f cpu = 3 mhz 1.8 5.5
S3CB018/fb018 s3fb0 18 20- 5 table 20-4. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit input high voltage v ih1 all input pins except v ih2 0.8 v dd ? v dd v v ih2 x in v dd - 0.1 input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v il2 x in 0.1 output high voltage v oh1 v dd = 5v; i oh = -1 ma all output pins v dd -1.0 ? ? v output low voltage v ol1 v dd = 5v; i ol = 8 ma all output pins except v ol2 ? ? 2 v ol2 v dd = 5v; i ol = 15 ma, port 1 2 input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 3 ua i lih2 v in = v dd x in , xt in 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? -3 i lil2 v in = 0 v x in , xt in , reset -20 output high leakage current i loh v out = v dd all i/o pins and output pins ? ? 3 ua output low leakage current i lol v out = 0 v all i/o pins and output pins ? ? -3 oscillator feed back resistors r osc1 (hsx) v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0v 510 710 910 k w r osc2 (msx) v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0v 510 710 910 r osc3 (lsx) v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0v 2.0 2.7 3.5 m w pull-up resistor r l1 v in = 0 v; v dd = 5 v 10% ports 0,1,2,3,4,5 t a =25 c 30 50 70 k w r l2 v in = 0 v; v dd = 5 v 10% t a =25 c, reset only 110 210 310
s3fb018 S3CB018/fb0 18 20- 6 table 20-4. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 (2) operating mode: v dd = 5 v 10% 20 mhz crystal oscillator(hsx) ? 10 20 ma 5 mhz crystal oscillator(msx) 4 8 v dd = 3 v 10% 5 mhz crystal oscillator(msx) 2 4 i dd2 (3) idle mode: v dd = 5 v 10% 20 mhz crystal oscillator(hsx) ? 2.5 5 ma 5 mhz crystal oscillator(msx) 1 2 v dd = 3 v 10% 5 mhz crystal oscillator(msx) 0.4 0.8 i dd3 stop mode v dd = 5 v 10% ? 0.5 3 ua v dd = 3 v 10% 0.2 1.2 notes: 1. supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. in operating current test mode timer a and timer b are running. 3. in idle current test mode the watch timer is running. 4. the operating and idle currents are measured at weak mode .

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